Researchers at the Indian Institute of Science (IISc) have develop a design framework to build next-generation analog computing chipsets that could be faster and require less power than the digital chips found in most electronic devices.
Using their novel design framework, the team has built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable Technology And Bias-scalable Hardware for AI Tasks), the Bengaluru-base IISc said in a statement.
As per Statement :
Most electronic devices, particularly those that involve computing, use digital chips because the design process is simple and scalable, it noted.
Chetan Singh Thakur, Assistant Professor at the Department of Electronic Systems Engineering (DESE), IISc, whose lab is leading the efforts to develop the analog chipset explain :
In applications that do not require precise calculations, analog computing has the potential to outperform digital computing as the former is more energy-efficient.
There are many technology hurdles to overcome while designing analog chips.
Unlike digital chips, testing and co-design of analog processors is difficult. Large-scale digital processors can be easily synthesise by compiling a high-level code, and the same design can be port across different generations of technology development say, from a 7 nm chipset to a 3 nm chipset with minimal modifications, the statement said.
Because analog chips don’t scale easily, they need to be individually customise when transitioning to the next generation technology or to a new application their design is expensive, it said.
Another challenge is that trading off precision and speed with power and area is not easy when it comes to analog design, it added.
In digital design, simply adding more components like logic units to the same chip can increase precision, and the power at which they operate can be adjust without affecting the device performance, the statement noted.
To overcome these challenges, the team has design a novel framework that allows the development of analog processors which scale just like digital processors.
Its chipset can be reconfigure and program so that the same analog modules can be port across different generations of process design and across different applications, it said.
Chetan Singh Thakur Said :
Different machine learning architectures can be program on ARYABHAT, and like digital processors, can operate robustly across a wide range of temperatures, the researchers said.
They added that the architecture is also “bias-scalable”, its performance remains the same when the operating conditions like voltage or current are modified.
This means that the same chipset can be configure for either ultra-energy-efficient Internet of Things (IoT) applications or for high-speed tasks like object detection.
The design framework was develop as part of IISc student Pratik Kumar’s PhD work, and in collaboration with Shantanu Chakrabartty, Professor at the McKelvey School of Engineering, Washington University in St Louis (WashU), US, who also serves as WashU’s McDonnell Academy ambassador to IISc.
Shantanu Chakrabartty Said :
The researchers have outline their findings in two pre-print studies that are currently under peer review.
They have also file patents and are planning to work with industry partners to commercialise the technology, the statement said.